Semiconductor device fabrication method

ABSTRACT

According to the present invention, there is provided a semiconductor device fabrication method having: coating a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, thereby forming a coating film; forming a polysilazane film by volatilizing the solvent by heat-treating the coating film; and inserting the semiconductor substrate into a predetermined furnace, lowering a pressure in the furnace, and oxidizing the polysilazane film while the pressure in the furnace is raised by supplying steam into the furnace, thereby forming a silicon oxide film.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims benefit of priority under 35USC §119 from the Japanese Patent Application No. 2005-33351, filed onFeb. 9, 2005, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device fabricationmethod.

Recently, to increase the degree of integration and the operating speedand reduce the power consumption and the fabrication cost,micropatterning of LSIs has advanced so that the minimum processingdimension (e.g., the gate length of a transistor) is nearly 0.1 μm. ThisLSI micropatterning is expected to advance in the future until theminimum processing dimension becomes 0.1 μm or less. For example, logicdevices in which the gate length of a transistor is decreased to about30 nm are developed.

To micropattern an element such as a transistor, it is important tomicropattern an element isolation region which occupies more than halfthe element area. Recently, an STI (Shallow Trench Isolation) method isused as a method of forming this element isolation region. In this STImethod, an element isolation trench is formed by etching the surfaceportion of a semiconductor substrate, and an element isolation region(i.e., an element isolation insulating film) is formed by burying aninsulating film in this element isolation trench. By the use of this STImethod, the width of an element isolation region reaches about 70 to 90nm smaller than 0.1 μm.

Also, in a memory requiring a high degree of integration, the widths ofboth an element formation region (active area) in which a transistor andthe like are formed and an element isolation region reach about 70 to 90nm smaller than 0.1 μm. In a memory like this, micropatterning of anelement isolation region is important.

On the other hand, micropatterning of elements makes the formation of anelement isolation region difficult. Separation between adjacent elementsis determined by the effective distance between the adjacent elements,i.e., the shortest distance (the depth of an element isolationtrench×2+the width of the element isolation trench) when a circuit ismade around an element isolation region.

Even when a device is micropatterned, therefore, the effective distance,i.e., the depth of an element isolation trench must be maintained inorder not to deteriorate the insulation properties of adjacent elements.Since, however, the width of an element isolation trench is decreased bymicropatterning, the aspect ratio (the depth of the element isolationtrench/the width of the element isolation trench) of the elementisolation trench increases as micropatterning advances. This makes itdifficult to bury an insulating film in the element isolation trench.

As a method of burying an insulating film in an element isolation trenchlike this, high-density plasma (HDP) CVD is used. When a silicon oxidefilm as an insulating film is to be buried in an element isolationtrench by using this high-density plasma CVD, the aspect ratio is 3 ormore if the minimum processing dimension is 0.1 μm or less. This resultsin the inconvenience that voids (unfilled portions) readily form in theinsulating film buried in the element isolation trench.

As a method of burying an insulating film in a micropatterned elementisolation trench, therefore, it is possible to form and bury an SOG(Spin On Glass) film by spin coating (by which a semiconductor substrateis coated with a predetermined solution while being rotated).

It is also possible to form and bury a silicon oxide film by reactingTEOS (Tetraethoxysilane) gas having fluidity with O₃ (ozone) gas.

In still another method, a silicon oxide film is buried in an elementisolation trench by using high-density plasma CVD, and a silicon oxidefilm formed by reacting TEOS gas with O₃ (ozone) gas is buried inportions not filled by high-density plasma CVD.

Recently, a semiconductor substrate is coated with a silazane perhydridepolymer solution so as to fill an element isolation trench formed in thesubstrate, and oxidation is performed in a steam ambient to form asilicon oxide film as an element isolation insulating film (e.g.,references 1 and 2).

More specifically, a silazane perhydride polymer solution is prepared bydispersing a silazane perhydride polymer ((SiH₂NH)_(n)) in a solventsuch as xylene (C₆H₄(CH₃)₂) or dibutylether ((C₄H₉)₂₀).

Then, the surface of a semiconductor substrate is coated with thissilazane perhydride polymer solution by spin coating so as to fill anelement isolation trench formed in the substrate. A predetermined heattreatment is performed on this coated silazane perhydride polymersolution to volatilize the solvent in it, thereby forming a polysilazanefilm. After that, the polysilazane film is oxidized to form a siliconoxide (SiO₂) film as an element isolation insulating film.

In the polysilazane film formed by volatilizing the solvent in thesilazane perhydride polymer solution, carbon (C) contained in thesolvent such as xylene (C₆H₄(CH₃)₂) or dibutylether ((C₄H₉)₂₀) remainsas an impurity.

Accordingly, to form a silicon oxide (SiO₂) film having high filmquality, it is necessary to remove carbon (C) as an impurity byincreasing the oxidation amount in the oxidation process. However, ifthe oxidation amount is increased while a silicon oxide film serving asa gate insulating film and a polysilicon film serving as a gateelectrode are formed in an element formation region (active area), thesesilicon oxide film and polysilicon film oxidize. As a consequence, theelectrical characteristics and reliability of the transistordeteriorate.

On the other hand, if the oxidation amount is decreased to suppressoxidation in this element formation region, an impurity such as carbon(C) remains in the silicon oxide (SiO₂) film and functions as positivefixed electric charge. Consequently, the electrical characteristics andreliability of the transistor deteriorate in this case as well.

References related to the element isolation insulating film formationmethod are as follows.

Reference 1: Japanese Patent Laid-Open No. 2004-179614

Reference 2: Japanese Patent Laid-Open No. 2002-367980

It is an object of the present invention to provide a semiconductordevice fabrication method capable of suppressing deterioration of theelectrical characteristics and reliability of a transistor.

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided asemiconductor device fabrication method comprising:

coating a semiconductor substrate with a silazane perhydride polymersolution prepared by dispersing a silazane perhydride polymer in asolvent containing carbon, thereby forming a coating film;

forming a polysilazane film by volatilizing the solvent by heat-treatingthe coating film; and

inserting the semiconductor substrate into a predetermined furnace,lowering a pressure in the furnace, and oxidizing the polysilazane filmwhile the pressure in the furnace is raised by supplying steam into thefurnace, thereby forming a silicon oxide film.

According to one aspect of the invention, there is provided asemiconductor device fabrication method comprising:

coating a semiconductor substrate with a predetermined solution preparedby dispersing a material containing silicon in a solvent containingcarbon, thereby forming a first film;

forming a second film by volatilizing the solvent by heat-treating thefirst film; and

inserting the semiconductor substrate into a predetermined furnace,lowering a pressure in the furnace, and oxidizing the second film whilethe pressure in the furnace is raised by supplying steam into thefurnace, thereby forming a silicon oxide film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of a semiconductor device fabricationmethod according to the first embodiment of the present invention;

FIG. 2 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method;

FIG. 3 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method;

FIG. 4 is a graph showing a change in pressure in a diffusion furnacewhen an oxidation process of the embodiment is performed;

FIG. 5 is a graph showing a change in pressure in a diffusion furnacewhen an oxidation process of a comparative example is performed;

FIG. 6 is a view showing the results of comparison when the oxidationprocesses of the embodiment and comparative example are performed;

FIG. 7 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of a semiconductor device fabricationmethod according to the second embodiment of the present invention;

FIG. 8 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method;

FIG. 9 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method;

FIG. 10 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method;

FIG. 11 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of a semiconductor device fabricationmethod according to another embodiment of the present invention;

FIG. 12 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method; and

FIG. 13 is a longitudinal sectional view showing an element sectionalstructure in a predetermined step of the same semiconductor devicefabrication method.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to the accompanying drawings.

(1) First Embodiment

FIGS. 1 to 3 show an element isolation insulating film formation methodaccording to the first embodiment of the present invention. As shown inFIG. 1, a silicon oxide (SiO₂) film 20 about 5 nm thick is formed on asemiconductor substrate 10 by thermal oxidation, and a silicon nitride(SiN) film 30 about 150 nm thick which serves as a stopper of polishingby CMP to be performed later is formed by CVD.

A silicon oxide (SiO₂) film (not shown) is formed on the entire surfaceof the silicon nitride (SiN) film 30 by CVD. This silicon oxide (SiO₂)film is coated with a photoresist (not shown), and exposure anddevelopment are performed to form a resist mask (not shown).

This resist mask is used as a mask to pattern the silicon oxide (SiO₂)film by RIE, thereby forming a hard mask. After that, the resist mask isremoved by an asher (an apparatus which removes a resist in a vaporphase), and etching using a solution mixture of sulfuric acid andaqueous hydrogen peroxide.

This hard mask is used as a mask to sequentially pattern the siliconnitride (SiN) film 30 and silicon oxide (SiO₂) film 20 by RIE. The hardmask is used as a mask again to etch the semiconductor substrate 10,thereby forming an element isolation trench 40 about 300 nm deep fromthe surface of the semiconductor substrate 10.

After the hard mask is removed by hydrofluoric acid steam (steamcontaining hydrofluoric acid), a silicon oxide (SiO₂) film 50 about 4 nmthick is formed on the inner surfaces of the element isolation trench 40by thermal oxidation.

Subsequently, a silazane perhydride polymer solution is prepared bydispersing a silazane perhydride polymer ((SiH₂NH)_(n)) in a solventsuch as xylene (C₆H₄(CH₃)₂) or dibutylether ((C₄H₉)₂₀).

As shown in FIG. 2, while the semiconductor substrate 10 is rotated, thesurface of the semiconductor substrate 10 is coated with the silazaneperhydride polymer solution by spin coating so as to fill the elementisolation trench 40 formed in the surface portion of the semiconductorsubstrate 10, thereby forming a coating film 60.

As described above, the surface is coated with the silazane perhydridepolymer solution as a liquid. Even when the aspect ratio of the elementisolation trench 40 is high, therefore, neither voids (unfilledportions) nor seams (seamed unfilled portions) are formed inside theelement isolation trench, unlike when a film is buried by usinghigh-density plasma CVD.

Examples of the spin coating conditions are that the rotational speed ofthe semiconductor substrate 10 is 4,000 rpm, the rotation time is 30sec, the dropping amount of the silazane perhydride polymer solution is8 cc, and the target film thickness of the coating film 60 is about 500nm.

The semiconductor substrate 10 having the coating film 60 is placed on ahotplate, and a heat treatment is performed such that the coating film60 is baked (heated) for 3 min in an inert gas ambient at a temperatureof 180° C.

Consequently, the solvent such as xylene (C₆H₄(CH₃)₂) or dibutylether((C₄H₉)₂₀) in the silazane perhydride polymer solution is volatilized toform a polysilazane film 70. In the polysilazane film 70, a few % toten-odd % of carbon (C) or hydrocarbon contained in the solvent remainsas an impurity.

The semiconductor substrate 10 having the polysilazane film 70 isinserted into a batch type diffusion furnace (not shown). In thisdiffusion furnace, the polysilazane film 70 is oxidized to form asilicon oxide (SiO₂) film 80 serving as an element isolation insulatingfilm.

FIG. 4 shows a change in pressure in the diffusion furnace from thetiming when the semiconductor substrate 10 is inserted into thediffusion furnace to the timing when the semiconductor substrate 10 isremoved from the diffusion furnace after oxidation is performed.

As shown in FIG. 4, the semiconductor substrate 10 is inserted into thediffusion furnace after the pressure in the diffusion furnace is set at760 Torr (atmospheric pressure) and the temperature is set at about 200°C. After that, the pressure in the diffusion furnace is lowered to 100Torr. In this case, the pressure in the diffusion furnace need only be100 Torr or less.

Subsequently, the temperature in the diffusion furnace is raised to,e.g., 200° C. to 500° C., and steam is supplied into the diffusionfurnace when 35 min have elapsed from the insertion of the semiconductorsubstrate 10. While the pressure in the diffusion furnace is raised to350 Torr over 5 min, the polysilazane film 70 is oxidized.

In this case, the pressure in the diffusion furnace need only be raisedso as to fall within the range of 200 to 700 Torr. Also, although thepressure raising rate at which the pressure in the diffusion furnace israised is set at 50 Torr/min, the pressure raising rate need only fallwithin the range of 50 to 100 Torr/min by adjusting the exhausting rateof a dry pump (not shown). In addition, the temperature in the diffusionfurnace when oxidation is performed need only be 200° C. to 800° C.

Furthermore, control for raising the pressure in the diffusion furnacemay also be performed by a pressure controller (not shown) of thediffusion furnace. It is also possible to prepare multiple pressuresteps and raise the pressure in the diffusion furnace stepwise.

While the pressure in the diffusion furnace is held at 350 Torr,oxidation is further performed in the steam ambient for 25 min toconvert the polysilazane film 70 into the silicon oxide (SiO₂) film 80.When 65 min have elapsed from the insertion of the semiconductorsubstrate 10, the supply of steam into the diffusion furnace is stopped,and evacuation is performed to once lower the pressure in the diffusionfurnace to 0 Torr. After that, the pressure in the diffusion furnace israised again and set at 760 Torr (atmospheric pressure), and thesemiconductor substrate 10 is removed from the diffusion furnace.

In this embodiment as described above, the pressure in the diffusionfurnace is lowered to allow impurities such as carbon (C) and nitrogen(N) to readily diffuse outside from the polysilazane film 70, and thenoxidation is performed while the pressure in the diffusion furnace israised by supplying steam. In this way, while the impurities such ascarbon (C) and nitrogen (N) contained in the polysilazane film 70 areremoved, Si—N bonds in the polysilazane film 70 are converted into Si—Obonds, thereby converting the polysilazane film 70 into the siliconoxide (SiO₂) film 80. Note that a reaction formula when the polysilazanefilm 70 is converted into the silicon oxide (SiO₂) film 80 isFormula 1 SiH₂NH+2O→SiO₂+NH₃  (1)

Since the impurities such as carbon (C) and nitrogen (N) contained inthe polysilazane film 70 are removed, the silicon oxide (SiO₂) film 80,obtained from the polysilazane film 70 is densified.

As a comparative example, FIG. 5 shows a change in pressure in thediffusion furnace when the semiconductor substrate 10 is inserted intothe diffusion furnace, the pressure in the diffusion furnace is loweredto 350 Torr, and oxidation is performed while the pressure in thediffusion furnace is kept unchanged and maintained at 350 Torr from thestart timing of supply of steam into the diffusion furnace to the endtiming of the supply of steam.

Note that a test substrate as a semiconductor substrate for checking theoxidation amount is set in the diffusion furnace. As shown in FIG. 6, inboth the oxidation processes performed by the comparative example andthis embodiment, the average value of the film thicknesses of siliconoxide (SiO₂) films formed on the test substrate is about 1.3 nm. Thatis, the oxidation amounts of these oxidation processes are substantiallythe same.

On the other hand, the concentration of carbon (C) in the silicon oxide(SiO₂) film 80 is 8×10¹⁹/cm³ in the comparative example and 2×10¹⁹/cm³in this embodiment. That is, the oxidation process by this embodimentcan greatly reduce the concentration of carbon (C) in the silicon oxide(SiO₂) film 80, compared to the oxidation process by the comparativeexample.

In this embodiment as described above, the concentration of carbon (C)which functions as positive fixed electric charge can be made much lowerthan that in the comparative example without increasing the oxidationamount of the oxidation process by the comparative example, i.e., withsubstantially the same oxidation amount as in the comparative example.Accordingly, the electric characteristics and reliability of thetransistor can be improved.

When the pressure in the diffusion furnace is low, the diffusion rate ofsteam supplied into the diffusion furnace increases, so the steamreadily diffuses. When steam is supplied by lowering the pressure in thediffusion furnace as in this embodiment, therefore, the steam welldiffuses not only in the peripheral portion of the semiconductorsubstrate 10 but also in its central portion.

For example, as shown in FIG. 6, the variation in film thickness of thesilicon oxide (SiO₂) film formed on the test substrate is 8% in theoxidation process by the comparative example, and 3% in the oxidationprocess by this embodiment. When the oxidation process by thisembodiment is used, therefore, the variation in film thickness of thesilicon oxide (SiO₂) film can be reduced compared to the oxidationprocess by the comparative example. This makes it possible to improvethe uniformity of the oxidation amount in the same semiconductorsubstrate.

Also, a plurality of semiconductor substrates are inserted into a batchtype diffusion furnace. Since, therefore, the oxidation process by thisembodiment allows easy diffusion of steam as described above, thevariations in film thickness of silicon oxide (SiO₂) films formed ondifferent semiconductor substrates can be made smaller than in theoxidation process by the comparative example. Accordingly, theuniformity of the oxidation amounts of different semiconductorsubstrates can be improved.

Then, the silicon oxide (SiO₂) film 80 is densified as it isheat-treated (annealed) in dry oxygen at a temperature of, e.g., 900° C.for 30 min.

As shown in FIG. 3, the silicon nitride (SiN) film 30 is used as astopper to polish the silicon oxide (SiO₂) film 80 to planarize itssurface by CMP, thereby exposing the silicon nitride (SiN) film 30.After the silicon nitride (SiN) film 30 is removed by using hotphosphoric acid obtained by heating phosphoric acid, predetermined stepsare performed to form an element such as a transistor on an elementformation region 10A of the semiconductor substrate 10.

Note that the first embodiment described above is merely an example, anddoes not limit the present invention. For example, filling need not beperformed by using the silazane perhydride polymer solution alone, andit is also possible to perform filling by using high-density plasma CVD,and fill portions, which are not filled by high-density plasma CVD, withthe silazane perhydride polymer solution.

(2) Second Embodiment

FIGS. 7 to 10 show an element isolation insulating film formation methodaccording to the second embodiment of the present invention. Note thatthis embodiment relates to the formation of an element isolationinsulating film for separating memory cell transistors of a NAND flashmemory. In this case, an element isolation insulating film is formedafter a floating gate electrode is formed on a semiconductor substratevia a tunnel insulating film.

As shown in FIG. 7, a silicon oxide (SiO₂) film 110 serving as a tunneloxide film is formed on a semiconductor substrate 100 by thermaloxidation. After that, a polysilicon film 120 serving as a floating gateelectrode is formed by CVD, and a silicon nitride (SiN) film 130 servingas a stopper of polishing by CMP to be performed later is formed.

In the same manner as in the first embodiment, a hard mask is formed andused as a mask to sequentially pattern the silicon nitride (SiN) film130, polysilicon film 120, and silicon oxide (SiO₂) film 110 by RIE.This hard mask is used as a mask again to etch the semiconductorsubstrate 100, thereby forming element isolation trenches 140A and 140Babout 200 nm deep from the surface of the semiconductor substrate 100.

After the hard mask is removed by hydrofluoric acid steam (steamcontaining hydrofluoric acid), a silicon oxide (SiO₂) film 150 about 4nm thick is formed on the inner surfaces of the element isolationtrenches 140A and 140B by thermal oxidation.

As shown in FIG. 8, high-density plasma CVD is used to form a siliconoxide (SiO₂) film 160 serving as an element isolation insulating film onthe silicon oxide (SiO₂) film 150 and silicon nitride (SiN) film 130 soas to fill the element isolation trenches 140A and 140B.

The silicon oxide (SiO₂) film 160 completely fills the element isolationtrench 140B having a low aspect ratio, but cannot completely fill theelement isolation trench 140A having a high aspect ratio. Consequently,a slit-like gap 170 remains in the element isolation trench 140A. Notethat the aspect ratio of the slit-like gap 170 is 10 or more, so it isdifficult to fill the gap 170 by high-density plasma CVD.

Subsequently, as in the first embodiment, a silazane perhydride polymersolution is prepared by dispersing a silazane perhydride polymer((SiH₂NH)_(n)) in a solvent such as xylene (C₆H₄(CH₃)₂) or dibutylether((C₄H₉)₂₀).

As shown in FIG. 9, while the semiconductor substrate 100 is rotated,the surface of the silicon oxide (SiO₂) film 160 is coated with thesilazane perhydride polymer solution by spin coating so as to fill thegap 170 formed in the silicon oxide (SiO₂) film 160, thereby forming acoating film 180.

As described above, even when the aspect ratio of the gap 170 formed inthe silicon oxide (SiO₂) film 160 is high, the gap 170 can be filled bycoating of the silazane perhydride polymer solution as a liquid, withoutforming any voids (unfilled portions) or seams (seamed unfilledportions). Note that the spin coating conditions are the same as in thefirst embodiment.

Following the same procedure as in the first embodiment, a predeterminedheat treatment is performed on the coating film 180 to volatilize thesolvent such as xylene (C₆H₄(CH₃)₂) or dibutylether ((C₄H₉)₂₀) in thesilazane perhydride polymer solution, thereby forming a polysilazanefilm 190. In this case, a few % to ten-odd % of carbon (C) orhydrocarbon contained in the solvent remains as an impurity.

The semiconductor substrate 100 having the polysilazane film 190 isinserted into a batch type diffusion furnace (not shown). In thisdiffusion furnace, the polysilazane film 190 is oxidized in the samemanner as in the first embodiment, thereby forming a silicon oxide(SiO₂) film 200 serving as an element isolation insulating film togetherwith the silicon oxide (SiO₂) film 160.

That is, the oxidation process is performed while the pressure in thediffusion furnace is raised by supplying steam into it. After thepressure in the diffusion furnace has risen to a predetermined pressure,the oxidation process is further performed for a predetermined timewhile this pressure is held, thereby converting the polysilazane film190 into the silicon oxide (SiO₂) film 200. The various conditions ofthe oxidation process are the same as in the first embodiment.

In this manner, the polysilazane film 190 is converted into the siliconoxide (SiO₂) film 200 while impurities such as carbon (C) and nitrogen(N) contained in the polysilazane film 190 are removed.

In this case, as in the first embodiment, the silicon oxide (SiO₂) film200 obtained from the polysilazane film 190 is densified becauseimpurities such as carbon (C) and nitrogen (N) contained in thepolysilazane film 190 are removed.

In this embodiment as described above, the concentration of carbon (C)which functions as positive fixed electric charge can be made much lowerthan that in a comparative example in which oxidation is performed withthe pressure in the diffusion furnace held constant, without increasingthe oxidation amount of the oxidation process by the comparativeexample, i.e., with substantially the same oxidation amount as in thecomparative example. Accordingly, the electric characteristics andreliability of the transistor can be improved.

Note that the oxidation amount need not be increased in this embodiment.This makes it possible to prevent a so-called bird's beak by which thefilm thickness of the edge of the silicon oxide (SiO₂) film 110 servingas a tunnel insulating film increases. It is also possible to preventdeterioration of the silicon oxide (SiO₂) film 110 caused by the heattreatment.

Furthermore, as in the first embodiment, it is possible to improve theuniformity of the oxidation amount in the same semiconductor substrate,and improve the uniformity of the oxidation amounts in differentsemiconductor substrates.

Then, as in the first embodiment, the silicon oxide (SiO₂) film 200 isdensified by a predetermined heat treatment (annealing).

As shown in FIG. 10, the silicon nitride (SiN) film 130 is used as astopper to polish the silicon oxide (SiO₂) films 160 and 200 toplanarize their surfaces by CMP, thereby exposing the silicon nitride(SiN) film 130. After that, the silicon nitride (SiN) film 130 isremoved by using hot phosphoric acid.

Finally, predetermined steps such as a step of forming a control gateelectrode (not shown) on the polysilicon film 120 as a floating gateelectrode via an insulating film are performed, thereby fabricating amemory cell transistor of a NAND flash memory.

Note that the second embodiment described above is merely an example,and does not limit the present invention.

For example, although the silicon oxide (SiO₂) film 160 is formed byhigh-density plasma CVD, an HTO (High Temperature Oxide) film may alsobe formed by thermal CVD. In addition, after filling is performed byusing high-density plasma CVD, the gap 170 which cannot be filled byhigh-density plasma CVD is filled with the silazane perhydride polymersolution. However, filling may also be performed by using the silazaneperhydride polymer solution alone.

(3) Another Embodiment

The above embodiments are merely examples, and do not limit the presentinvention. For example, the oxidation processes of the first and secondembodiments may also be applied to the formation of not an elementisolation insulating film but an interlayer dielectric film. FIGS. 11 to13 show an interlayer dielectric film formation method according toanother embodiment of the present invention.

As shown in FIG. 11, element isolation insulating films 310A and 310Bare formed on a semiconductor substrate 300, and a gate insulating film320 and gate electrode 330 are formed. Then, a source extension region340A, a drain extension region 340B, gate electrode side walls 350A and350B, a source region 360A, and a drain region 360B are sequentiallyformed.

After that, a metal film of, e.g., nickel (Ni), cobalt (Co), or lead(Pb) is formed by sputtering, and annealing is performed to formsilicide films 370A to 370C for reducing the parasitic resistance in thesurface portions of the gate electrode 330, source region 360A, anddrain region 360B.

As shown in FIG. 12, a silicon nitride (SiN) film 380 serving as anetching stopper when contact holes are formed later is formed.

Subsequently, as in the first embodiment, a silazane perhydride polymersolution is prepared by dispersing a silazane perhydride polymer((SiH₂NH)_(n)) in a solvent such as xylene (C₆H₄(CH₃)₂) or dibutylether((C₄H₉)₂₀).

While the semiconductor substrate 300 is rotated, the surface of thesilicon nitride (SiN) film 380 is coated with the silazane perhydridepolymer solution by spin coating, thereby forming a coating film 390.Note that the spin coating conditions are the same as in the firstembodiment.

Following the same procedure as in the first embodiment, a predeterminedheat treatment is performed on the coating film 390 to volatilize thesolvent such as a xylene (C₆H₄(CH₃)₂) or dibutylether ((C₄H₉)₂₀) in thesilazane perhydride polymer solution, thereby forming a polysilazanefilm 400. In this case, a few % to ten-odd % of carbon (C) orhydrocarbon contained in the solvent remains as an impurity in thepolysilazane film 400.

The semiconductor substrate 300 having the polysilazane film 400 isinserted into a batch type diffusion furnace (not shown). In thisdiffusion furnace, the polysilazane film 400 is oxidized in the samemanner as in the first embodiment, thereby forming a silicon oxide(SiO₂) film 410 serving as an interlayer dielectric film.

That is, the oxidation process is performed while the pressure in thediffusion furnace is raised by supplying steam into it. After thepressure in the diffusion furnace has risen to a predetermined pressure,the oxidation process is further performed for a predetermined timewhile this pressure is held, thereby converting the polysilazane film400 into the silicon oxide (SiO₂) film 410. The various conditions ofthe oxidation process are the same as in the first embodiment exceptthat the temperature in the diffusion furnace is adjusted to fall withinthe range of 200° C. to 500° C.

In this manner, the polysilazane film 400 is converted into the siliconoxide (SiO₂) film 410 while impurities such as carbon (C) and nitrogen(N) contained in the polysilazane film 400 are removed.

If the silicon oxide (SiO₂) film 410 as an interlayer dielectric film isformed at a high temperature of, e.g., 500° C. or more, the silicidefilms 370A to 370C aggregate, and this increases the resistance of thesefilms. Therefore, an interlayer dielectric film must be formed at a lowtemperature. For example, when the silicide films 370A to 370C are madeof nickel silicide, an interlayer dielectric film must be formed at atemperature of 500° C. or less.

If, for example, high-density plasma CVD is used, an interlayerdielectric film can be formed at a low temperature. However, if aninterlayer dielectric film is thus formed by high-density plasma CVD,so-called plasma damage is inflicted on the silicon nitride (SiN) film380 serving as an etching stopper, and the film quality of the siliconnitride (SiN) film 380 deteriorates.

By contrast, in this embodiment, an interlayer dielectric film can beformed at a low temperature, and this prevents the increase inresistance of the silicide films 370A to 370C. Also, unlike inhigh-density plasma CVD, no plasma damage is inflicted on the siliconnitride (SiN) film 380 serving as an etching stopper. This preventsdeterioration of the film quality of the silicon nitride (SiN) film 380.

As shown in FIG. 13, contact holes (not shown) are formed by etching thesilicon oxide (SiO₂) film 410 by using the silicon nitride (SiN) film380 as an etching stopper. After that, portions of the upper surfaces ofthe silicide films 370A to 370C are exposed by forming holes in thesilicon nitride (SiN) film 380 by etching.

Contact plugs 420 are formed by burying tungsten or the like in thesecontact holes. After that, an interconnection 430 made of, e.g.,aluminum is formed on the silicon oxide (SiO₂) film 410 and contactplugs 420.

The semiconductor device fabrication method of the above embodiment canprevent deterioration of the electrical characteristics and reliabilityof the transistor.

1.-19. (canceled)
 20. A semiconductor device fabrication methodcomprising: forming a coating film over a semiconductor substrate with asilazane perhydride polymer solution prepared by dispersing a silazaneperhydride polymer in a solvent containing carbon; forming apolysilazane film by volatilizing the solvent by heat treating thecoating film; inserting the semiconductor substrate into a predeterminedfurnace, and lowering a pressure in the furnace to a predetermined firstvalue; and oxidizing the polysilazane film in steam atmosphere whileraising the pressure in the furnace to a predetermined second value,thereby forming a silicon oxide film.
 21. A semiconductor devicefabricating method comprising: forming a first film over a semiconductorsubstrate with a predetermined solution prepared by dispersing amaterial containing silicon in a solvent containing carbon; forming asecond film by volatilizing the solvent by heat treating the first film;inserting the semiconductor substrate into a predetermined furnace, andlowering a pressure in the furnace to a predetermined first value; andoxidizing the second film in steam atmosphere while raising the pressurein the furnace to a predetermined second value, thereby forming asilicon oxide film.
 22. A semiconductor device fabricating methodcomprising: forming a first film over a semiconductor substrate with apredetermined solution prepared by dispersing a material containingsilicon in a solvent containing carbon; forming a second film byvolatilizing the solvent by heat treating the first film; and oxidizingthe second film in steam atmosphere of a predetermined furnace while apressure in the furnace is raised, thereby forming a silicon oxide film.23. A method according to claim 20, wherein after the pressure in thefurnace is raised to the second value, oxidation is further performedfor a predetermined time while the pressure is held at the second value.24. A method according to claim 21, wherein after the pressure in thefurnace is raised to the second value, oxidation is further performedfor a predetermined time while the pressure is held at the second value.25. A method according to claim 22, wherein after the pressure in thefurnace is raised to the second value, oxidation is further performedfor a predetermined time while the pressure is held at the second value.26. A method according to claim 21, further comprising: forming asemiconductor element including a gate electrode above the semiconductorsubstrate, wherein when the first film is formed over the gateelectrode, the first film serves as an interlayer dielectric film.
 27. Amethod according to claim 22, further comprising: forming asemiconductor element including a gate electrode above the semiconductorsubstrate, wherein when the first film is formed over the gateelectrode, the first film serves as an interlayer dielectric film.
 28. Amethod according to claim 26, further comprising: forming a sourceregion and a drain region in surface portions of the semiconductorsubstrate; and forming silicide films on surface portions of the sourceregion and the drain region, or on a surface portion of the gateelectrode.
 29. A method according to claim 27, further comprising:forming a source region and a drain region in surface portions of thesemiconductor substrate; and forming silicide films on surface portionsof the source region and the drain region, or on a surface portion ofthe gate electrode.